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8-33 8 front-ends preliminary product description ordering information typical applications features functional block diagram rf micro devices, inc. 7628 thorndike road greensboro, nc 27409, usa tel (336) 664 1233 fax (336) 664 0454 http://www.rfmd.com optimum technology matching? applied si bjt gaas mesfet gaas hbt si bi-cmos sige hbt si cmos 19 nc 18 nc 17 lna gain 16 mix gain 14 iset1 13 iset2 12 mix in 10 nc if- 9 8 nc 7 if+ 5 nc 4 lo in 3 vcc2 2 vcc1 1 enable * * * * 20 lna in nc 6 11 lna2 e 15 lna out * represents "gnd". RF2460 pcs cdma low noise amplifier/mixer 1500mhz to 2200mhz downconverter ? cdma pcs handsets gps receiver w-cdma handsets general purpose downconverter commercial and consumer systems portable battery-powered equipment the RF2460 is a receiver front-end designed for the receive section of pcs cdma and w-cdma applica- tions. it is designed to amplify and downconvert rf sig- nals while providing 29db of stepped gain control range and features digital control of lna gain, mixer gain, and power down mode. a further feature of the chip is adjust- able iip3 of the lna and mixer using an off-chip current setting resistor. noise figure, ip3, and other specs are designed to be compatible with the is-98b for cdma pcs communications. the ic is manufactured on a sigehbt process and packaged in a 20-pin leadless chip carrier with an exposed die flag. complete receiver front-end stepped lna/mixer gain control adjustable lna/mixer bias current 24db gain and 2.2db noise figure at maximum cascade gain RF2460 pcs cdma low noise amplifier/mixer 1500mhz to 2200mhz downconverter RF2460 pcba fully assembled evaluation board 8 rev a7 010912 1.00 0.90 4.00 sq. 0.60 0.24 typ 3 0.20 0.75 0.50 0.23 0.13 4plcs 0.50 2.10 sq. 0.65 0.30 4plcs 0.05 12 max dimensions in mm. note orientation of package. notes: package warpage: 0.05 mm max. 4 die thickness allowable: 0.305 mm max. 5 pin 1 identifier must exist on top surface of package by identification mark or feature on the package body. exact shape and size is optional. 2 shaded lead is pin 1. 1 dimension applies to plated terminal: to be measured between 0.02 mm and 0.25 mm from terminal end. 3 package style: lcc, 20-pin, 4x4
preliminary 8-34 RF2460 rev a7 010912 8 front-ends absolute maximum ratings parameter rating unit supply voltage -0.5 to +5.0 v dc input lo and rf levels +6 dbm operating ambient temperature -40 to +85 c storage temperature -40 to +150 c parameter specification unit condition min. typ. max. overall t=25c, v cc =2.75v, rf=1.96ghz, lo=2170mhz@-7dbm, if=210mhz rf frequency range 1500 to 2200 mhz lo frequency range 1200 to 2600 mhz if frequency range 0.1 to 250 mhz bias current 2.5 2.8 ma lna, mixer and preamp for bias circuitry. lna gain 13.5 15.0 db noise figure 1.4 1.8 db input ip3 +6.0 +7.0 dbm iip3 is adjustable (see plots for setting). iset1 (pin 14) external resistor sets current consumption and performance. input vswr 2:1 output vswr 2:1 current at input ip3 7 7.5 ma lna bypass gain -6 -5 db noise figure 5 5.5 db input ip3 +23.0 +26.0 dbm input vswr 2:1 output vswr 2:1 current 0 ma mixer - high gain mode 1k ? balanced load. gain 10 12 db noise figure 6.5 7.5 db input ip3 +3.0 +4.0 dbm iip3 is adjustable (see plots for setting). rf to if isolation >45 db iset2 (pin 13) external resistor sets current consumption and performance. input vswr 2:1 output vswr 2:1 current 12 13 ma mixer - low gain mode 1k ? balanced load. gain 0 1.5 db noise figure 15 16 db input ip3 +13.0 +14.0 dbm iip3 is adjustable rf to if isolation >45 db iset2 (pin 13) external resistor sets current consumption and performance. input vswr 2:1 output vswr 2:1 current 7.5 8.0 ma caution! esd sensitive device. rf micro devices believes the furnished information is correct and accurate at the time of this printing. however, rf micro devices reserves the right to make changes to its products without notice. rf micro devices does not assume responsibility for the use of the described product(s).
preliminary 8-35 RF2460 rev a7 010912 8 front-ends parameter specification unit condition min. typ. max. gps - lna gain 16 db noise figure 1.4 db input ip3 +7.0 dbm iip3 is adjustable. iset1 (pin 14) external resistor sets current consumption and per- formance. current at input ip3 7 ma gps - mixer gain 17 db noise figure 6 db input ip3 -5.0 dbm iip3 is adjustable. iset1 (pin 14) external resistor sets current consumption and per- formance. current at input ip3 16 ma gps - cascaded gain 31 db noise figure 2.0 db input ip3 -1.0 dbm iip3 is adjustable. iset1 (pin 14) external resistor sets current consumption and per- formance. current at input ip3 23 ma local oscillator input input level -10 -7 0 dbm lo to rf isolation >40 db any gain state. lo to lna isolation >60 db any gain state. lo current buffer 4.5 5.0 ma i cc2 when lo signal is present cascade - lna high/mixer high lna high gain/mixer high gain assuming 3db loss of filter gain 24 db if 1, 1k ? balanced load. noise figure 2.2 db input ip3 -8.0 dbm single sideband. total current 26 ma cascade - lna high/mixer low lna high gain/mixer low gain assuming 3db loss of filter gain 13.5 db if 1, 1k ? balanced load. noise figure 5.3 db input ip3 +1.0 dbm single sideband. total current 21 ma cascade - lna low/mixer high lna low gain/mixer high gain assuming 3db loss of filter gain 4 db if 1, 1k ? balanced load. noise figure 14.5 db input ip3 +12.0 db single sideband. total current 19 ma cascade - lna low/mixer low lna low gain/mixer low gain assuming 3db loss of filter gain -6.5 db if 1, 1k ? balanced load. noise figure 23 db input ip3 +20.5 db single sideband. total current 14 ma power supply voltage 2.7 3.0 3.3 v
preliminary 8-36 RF2460 rev a7 010912 8 front-ends pin function description interface schematic 1 enable power down pin. a logic ?low? turns the part off. a logic ?high? (>1.6v) turns the part on. 2 vcc1 supply voltage for the lna, mixer, bias, and logic circuitry. external rf and if bypassing is required. the trace length between the pin and the bypass capacitors should be minimized. the ground side of the bypass capacitors should connect immediately to ground plane. see pin 20. 3 vcc2 supply voltage for the lo buffer amplifier. external rf and if bypass- ing is required. the trace length between the pin and the bypass capacitors should be minimized. the ground side of the bypass capaci- tors should connect immediately to ground plane. 4loin mixer lo input pin. 5nc no connection. for isolation purposes, this pin is connected to the ground plane. 6nc no connection. for isolation purposes, this pin is connected to the ground plane. 7if+ cdma if output pin. this is a balanced output. the internal circuitry, in conjunction with an external matching/bias inductor to v cc , sets the operating impedance. this inductor is typically incorporated in the matching network between the output and if filter. the part is designed todrivea1k ? load. because this pin is biased to v cc , a dc blocking capacitor must be used if the if filter input has a dc path to ground. see application schematic. 8nc no connection. for isolation purposes, this pin is connected to the ground plane. 9if- same as pin 7, except complementary output. see pin 6. 10 nc no connection. for isolation purposes, this pin is connected to the ground plane. 11 lna2 e emitter for lna2. increasing the inductance on this pin will reduce the mixer gain, increase ip3 and noise figure. 12 mix in mixer rf input pin. this pin is internally dc biased and should be dc blocked if connected to a device with dc present. external matching network sets rf and if impedance for optimum performance. 13 iset2 this pin is used to set the bias current and iip3 of the mixer amplifier using a resistor to ground. see plots for values and current settings. 14 iset1 this pin is used to set the bias current and iip3 of the lna amplifier using a resistor to ground. see plots for values and current settings. 15 lna out lna output pin. open collector. see pin 20. 16 mix gain cmos compatible signal controlling mixer gain mode. setting this sig- nal high places the mixer in the high gain mode. setting this signal low places the mixer in low gain mode by bypassing and shutting off the mixerbufferamplifiercurrent. 17 lna gain cmos compatible signal controlling lna gain mode. setting this signal high places the lna in the high gain mode. setting this signal low bypasses the lna and shuts off the lna bias current. 18 nc no connection. for isolation purposes, this pin is connected to the ground plane. 19 nc no connection. for isolation purposes, this pin is connected to the ground plane. if1- if1+ 1.2 pf 1.2 pf gnd2 mix in mix gain lna gain
preliminary 8-37 RF2460 rev a7 010912 8 front-ends pin function description interface schematic 20 lna in rf input pin. this pin is internally matched for optimum noise figure from a 50 ? source. pkg base gnd ground connection. the backside of the package should be soldered to a top side ground pad which is connected to the ground plane with mul- tiple vias. lna out lna in v cc1
preliminary 8-38 RF2460 rev a7 010912 8 front-ends application schematic - us pcs 82 ? 7.5 nh lna gain mix gain c1 c3 r c1 l2 0.1 f 0.1 f 47 nh 9.1 k ? 18 k ? 2nh 19 nh 510 ? 10 ? 0.1 f 19 18 17 16 14 13 12 10 9 8 7 5 4 3 2 1 * * * * 20 6 11 15 * represents "gnd". l1 c2 1nh 10 nh 22 pf enable lo in v cc2 v cc1 c3 0.1 f vcc1 c4 0.1 f vcc2 c3 and c4 should be placed as closely as possible to pins 2 and 3 v cc1 if out mix in lna out v cc1 0.1 f lna in 8 110 3 6 82 4.7 k us pcs, if = 184 mhz 4 82 3 5 150 3k gps, if = 184 mhz 3.6 120 2 7 82 4.7 k korean pcs, if = 220 mhz 4 110 3 6 82 4.7 k us pcs, if = 210 mhz c1 (pf) l2 (nh) c2 (pf) c3 (pf) l1 (nh) r( ? )
preliminary 8-39 RF2460 rev a7 010912 8 front-ends output interface network of the mixer l1, c1, c2, and r form a current combiner which per- forms a differential to single-ended conversion at the if frequency and sets the output impedance. in most cases, the resonance frequency is independent of r and can be set according to the following equation: where c eq is the equivalent stray capacitance and capacitance looking into pins 7 and 9. an average value to use for c eq is 2.5pf. r can then be used to set the output impedance according to the following equation: where r out is the desired output impedance and r p is the parasitic equivalent parallel resistance of l1. c 2 should first be set to 0 and c1 should be chosen as high as possible (suggested less than 20pf), while maintaining an r p of l1 that allows for the desired r out . if the self-resonant frequencies of the selected c1 produce unsatisfactory linearity performance, their values may be reduced and compensated for by including c2 capacitor with a value chosen to maintain the desired f if frequency. l2 and c3 serve dual purposes. l2 serves as an out- put bias choke, and c3 serves as a series dc block. in addition, l2 and c3 may be chosen to form an impedance matching network if the input impedance of the if filter is not equal to r out .otherwise,l2ischo- sen to be large (suggested 120nh) and c3 is chosen to be large (suggested 22nf) if a dc path to ground is present in the if filter, or omitted if the filter is dc blocked. f if 1 l 1 2 ------ c 1 2 c 2 c eq ++ () 2 ----------------------------------------------------------- = r 1 4 r out ? -------------------- - 1 r p ------ ? 1 ? =
preliminary 8-40 RF2460 rev a7 010912 8 front-ends application schematic - w-cdma (see w-cdma charts for lab measurements at the end of the data sheet) 19 18 17 16 14 13 12 10 9 8 7 5 4 3 2 1 * * * * 20 6 11 15 enable vcc1 vcc2 50 ? strip r1 82 ? l2 7.5 nh 50 ? strip 50 ? strip c7 4.3 pf c8 4.3 pf 50 ? strip 50 ? strip c9 4.3 pf l4 82 nh r2 dni 50 ? strip l3 150 nh c5 0.1 f vcc1 c6 5.6 pf 50 ? strip l5 1.0 nh 50 ? strip c10 0.1 f 50 ? strip l6 47 nh r3 9.1 k ? r6 18 k ? 50 ? strip l7 2.0 nh c11 22 pf 50 ? strip l8 19 nh r4 510 ? r5 10 ? c12 0.1 f vcc1 mix_gain lna_gain 50 ? strip c2 0.1 f 50 ? strip l1 10 nh RF2460pcba-u wcdma rf @ 2.14 ghz, lo @ 2.33 ghz, if @ 190 mhz if=190 mhz c3 0.1 f vcc1 c4 0.1 f vcc2 c2andc3shouldbeplacedas closely as possible to pins 2 and 3 p1 1 2 3 con3 p1-1 vcc1 gnd c1 1 f + p1-3 c13 1 f + lo in lna in lna out mix in if out p2 1 2 3 con3 p2-1 enable lna_gain p2-3 mix_gain p2-1
preliminary 8-41 RF2460 rev a7 010912 8 front-ends application schematic - gps rf=1575mhz, if=184mhz, lo=1759mhz enable 50 ? strip 82 ? 7.5 nh lna gain mix gain 50 ? strip 50 ? strip 4pf 5pf 50 ? strip 50 ? strip 50 ? strip 4pf 82 nh 50 ? strip .1 uf ***323 ps electrical delay*** ***0.03 db line loss*** 1.8 nh 50 ? strip 33 nf 50 ? strip 50 ? strip 10 nh ***397 ps electrical delay*** ***0.26 db line loss*** 9.1 k ? 8.2 k ? 50 ? strip 5.6 nh 22 pf 50 ? strip ***359 ps electrical delay*** ***0.23 db line loss*** 10 nh dnp 10 ? 0.1 uf 50 ? strip 6pf 50 ? strip 4.7 nh 50 ? strip ***c2 & c3 should be placed as closeaspossibletopins2&3*** ***390 ps electrical delay*** ***0.28 db line loss*** ***439 ps electrical delay*** ***0.33 db line loss*** 19 18 17 16 14 13 12 10 9 8 7 5 4 3 2 1 * * * * 20 6 11 15 * represents "gnd". 3pf 150 nh 3k ? vcc1 vcc2 if out v cc1 lo in lna in v cc1 lna out mix in
preliminary 8-42 RF2460 rev a7 010912 8 front-ends current measurement to measure only the current of the different circuitry in the evaluation board, use the following procedure. first, replace the bias choke inductor at the output of the mixer (l3 for us-pcs) with a 1 ? resistor. the voltage across the resistor will represent the mixer current. terminate all sma connections at 50 ? . second, follow the table below. therefore , condition current (ma) v cc1 v cc2 en lna gain mix gain i cc total 25.8211111 lna off 18.7711101 mixer preamp off 14.2811100 v cc2 off 10.0510100 mixer current 7.7210100 lna (bypass) = (computer simulation) = 0ma lna (high gain) = 25.82-18.77 = 7.05ma mixer (preamp) = 18.77-14.28 = 4.49ma mixer = (measured) = 7.70ma bias = 10.05-7.7 = 2.35ma lo circuitry (v cc2 ) = 14.28-10.05 = 4.23ma 25.82ma
preliminary 8-43 RF2460 rev a7 010912 8 front-ends evaluation board schematic us-pcs, if=210mhz (download bill of materials from www.rfmd.com.) enable r1 82 ? l2 7.5 nh j2 lo in lna gain mix gain c7 4pf c6 6pf j3 if out r2 4.7 k ? c9 4pf l3 110 nh vcc1 c5 0.1 f ***323 ps electrical delay*** ***0.03 db line loss*** c10 0.1 f l6 47 nh j4 mix in ***397 ps electrical delay*** ***0.26 db line loss*** r3 9.1 k ? r6 18 k ? l7 2nh j5 lna out ***359 ps electrical delay*** ***0.23 db line loss*** l8 19 nh r4 510 ? r5 10 ? c12 0.1 f vcc1 c2 0.1 f j1 lna in ***c3 and c4 should be placed as close as possible to pins 2 and 3*** ***390 ps electrical delay*** ***0.28 db line loss*** ***439 ps electrical delay*** ***0.33 db line loss*** 19 18 17 16 14 13 12 10 9 8 7 5 4 3 2 1 * * * * 20 6 11 15 * represents "gnd". p2 1 2 3 con3 p2-3 mix gain p2-2 lna gain p2-1 enable l4 82 nh c8 3pf p1 1 2 3 con3 gnd p1-1 c1 0.1 f vcc1 p1-3 c13 0.1 f vcc2 vcc1 vcc1 l5 1nh c3 0.1 f c4 0.1 f l1 10 nh c11 22 pf
preliminary 8-44 RF2460 rev a7 010912 8 front-ends evaluation board schematic korean-pcs, if = 220 mhz enable r1 68 ? l3 9nh j2 lo in lna gain mix gain c8 3.6 pf c7 7pf j3 if out r2 4.7 k ? c10 3.6 pf l4 120 nh vcc1 c6 0.1 f ***291 ps electrical delay*** ***0.05 db line loss*** c11 0.1 f l7 47 nh j4 mix in ***399 ps electrical delay*** ***0.32 db line loss*** r3 7.5 k ? r6 24 k ? l8 2.2 nh j5 lna out ***358 ps electrical delay*** ***0.26 db line loss*** l9 8.2 nh r4 510 ? r5 20 ? vcc1 c3 0.1 f j1 lna in ***c4 and c5 should be placed as close as possible to pins 2 and 3*** ***396 ps electrical delay*** ***0.30 db line loss*** ***400 ps electrical delay*** ***0.30 db line loss*** 19 18 17 16 14 13 12 10 9 8 7 5 4 3 2 1 * * * * 20 6 11 15 * represents "gnd". p2 1 2 3 con3 p2-3 mix gain p2-2 lna gain p2-1 enable l5 82 nh c9 2pf p1 1 2 3 con3 gnd p1-1 c1 0.1 f vcc1 p1-3 c14 0.1 f vcc2 vcc1 vcc1 l6 1nh l1 1.6 nh l2 10 nh c2 1pf c4 0.1 f c5 0.1 f c12 22 pf c13 0.1 f 2460310, rev. 5
preliminary 8-45 RF2460 rev a7 010912 8 front-ends evaluation board layout - us pcs board size 2.0" x 2.0" board thickness 0.034?, board material fr-4, multi-layer assembly top power plane 1 power plane 2
preliminary 8-46 RF2460 rev a7 010912 8 front-ends back
preliminary 8-47 RF2460 rev a7 010912 8 front-ends evaluation board layout - korean pcs assembly top power plane 1 power plane 2 back
preliminary 8-48 RF2460 rev a7 010912 8 front-ends special instructions (board loss, taking into consideration description in the schematic) lna v cc1 =v cc2 =enable=2.75v; mix gain=0.0v to measure i cc lna only: lna gain was switched between 0v and 2.75v, and record the delta current. mixer v cc1 =v cc2 =enable=mix gain=2.75v; lna gain=0.0v to measure i cc mixer (lna should be in bypass mode and lo signal should be present): to t a l m i xe r c u r r e n t = i cc1 v cc2 only affects lo current buffer and r6 doesn?t affect the mixer current. lnagain,noisefigureandiip3versusi cc -lnaonly (lna high gain) 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0 1.0 3.0 5.0 7.0 9.0 11.0 13.0 15.0 17.0 i cc (ma) gain and noise figure (db) -15.0 -10.0 -5.0 0.0 5.0 10.0 15.0 iip3 (dbm) gain (db) nf (db) iip3 (dbm) mixer gain, noise figure and iip3 versus i cc -mixer (mixer high gain, lo = -7 dbm) -20.0 -15.0 -10.0 -5.0 0.0 5.0 10.0 15.0 20.0 25.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0 i cc (ma) gain and noise figure (db) -15.0 -10.0 -5.0 0.0 5.0 10.0 iip3 (dbm) gain (db) nf (db) iip3 (dbm) resistor (r6) versus i cc (ma) - lna only (lna high gain) 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0 160.0 180.0 200.0 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 i cc (ma) resistor r6 (k ? ) resistor (r3) versus i cc - mixer (mixer high gain, lo = 2170 @ -7 dbm) 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0 160.0 180.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0 i cc (ma) resistor r3 (k ? ) us-pcs
preliminary 8-49 RF2460 rev a7 010912 8 front-ends instructions (board loss, taking into consideration description in the w-cdma schematic) lna i cc lna current=total current (v cc =lna gain=2.75)-total current (v cc =2.75; lna gain=0) to measure i cc lna only: lna gain was switched between 0v and 2.75v, and record the delta current. mixer i cc mix and bias current=total current (v cc ;=en=v cc2 =mix gain=2.75; lna gain=0)-total current (v cc ;=en=2.75; mix gain=lna gain=v cc2 =0 lo signal should be present. v cc2 only affects lo current buffer and r6 doesn?t affect the mixer current. lna gain, noise figure, and iip3 versus i cc -lnaonly (lna high gain) -10.00 -5.00 0.00 5.00 10.00 15.00 20.00 1.00 3.00 5.00 7.00 9.00 11.00 13.00 15.00 17.00 i cc (ma) gain (db) and iip3 (dbm) 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00 nf (db) gain (db) iip3 (dbm) nf (dbm) mixer gain, noise figure and iip3 versus i cc - mixer and bias circuits (mixer high gain, lo=-7dbm) -8.00 -6.00 -4.00 -2.00 0.00 2.00 4.00 6.00 8.00 10.00 12.00 14.00 6.00 6.50 7.00 7.50 8.00 8.50 9.00 9.50 10.00 i cc (ma) gain (db) and iip3 (dbm) 0.00 2.00 4.00 6.00 8.00 10.00 12.00 nf (db) gain (db) iip3 (dbm) nf (dbm) r6 versus i cc for lna 0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 80.0 90.0 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 i cc (ma) r6 (ma) r3 versus i cc for mixer and bias circuits 0.0 5.0 10.0 15.0 20.0 25.0 30.0 35.0 40.0 10.0 12.0 14.0 16.0 18.0 20.0 22.0 24.0 i cc (ma) r3 (k ? ) w-cdma (see w-cdma application schematic)
preliminary 8-50 RF2460 rev a7 010912 8 front-ends by using a r6=39k ? and r3=24k ? , the following results were obtained. rf=2140mhz, lo=2330mhz, if=190mhz. lna (high gain mode) wcdma 12.00 12.20 12.40 12.60 12.80 13.00 13.20 13.40 13.60 13.80 14.00 2.75 2.85 2.95 3.05 3.15 3.25 v cc (v) gain (db) gain, -30o gain, 25o gain, 85o lna (high gain mode) w-cdma 4.00 5.00 6.00 7.00 8.00 9.00 10.00 2.75 2.85 2.95 3.05 3.15 3.25 3.35 v cc (v) iip3 (dbm) iip3, -30o iip3, 25o iip3, 85o lna (high gain mode) w-cdma 0.00 0.50 1.00 1.50 2.00 2.50 2.75 2.85 2.95 3.05 3.15 3.25 3.35 v cc (v) noise figure (db) nf, -30o nf, 25o nf, 85o lna current w-cdma 3.90 3.95 4.00 4.05 4.10 4.15 4.20 4.25 4.30 4.35 2.75 2.85 2.95 3.05 3.15 3.25 3.35 v cc (v) i cc (ma) icc, -30o icc, 25o icc, 85o
preliminary 8-51 RF2460 rev a7 010912 8 front-ends mixer high gain mode, lo @ -7 dbm w-cdma 8.00 9.00 10.00 11.00 12.00 13.00 14.00 2.75 2.85 2.95 3.05 3.15 3.25 3.35 v cc (v) gain (db) gain, -30o gain, 25o gain, 85o mixer high gain mode, lo @ -7 dbm w-cdma 8.00 8.50 9.00 9.50 10.00 10.50 11.00 2.75 2.85 2.95 3.05 3.15 3.25 3.35 v cc (v) noise figure (db) nf, -30o nf, 25o nf, 85o mixer high gain mode, v cc @2.75w-cdma 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 12.5 13.0 -10.0 -9.0 -8.0 -7.0 -6.0 -5.0 -4.0 -3.0 lo (dbm) gain (db) gain, -30o gain, 25o gain, 85o mixerifhighgainmode, v cc @2.75w-cdma -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 -10.0 -9.0 -8.0 -7.0 -6.0 -5.0 -4.0 -3.0 lo (dbm) iip3 (dbm) iip3, -30o iip3, 25o iip3, 85o mixerifhighgainmode, v cc @2.75w-cdma 8.0 8.5 9.0 9.5 10.0 10.5 11.0 -10.0 -8.0 -6.0 -4.0 -2.0 0.0 lo (dbm) noise figure (db) nf, -30o nf, 25o nf, 85o mixerifhighgainmode, v cc @2.75w-cdma 5.5 5.6 5.7 5.8 5.9 6.0 6.1 6.2 -10.0 -8.0 -6.0 -4.0 -2.0 0.0 lo (dbm) i cc mixer and bias current (ma) icc, -30o icc, 25o icc, 85o
preliminary 8-52 RF2460 rev a7 010912 8 front-ends mixerifhighgainmode, lo @ -7 dbm w-cdma 5.00 5.50 6.00 6.50 7.00 7.50 2.75 2.85 2.95 3.05 3.15 3.25 3.35 v cc (v) i cc mixer and bias circuit (ma) icc, -30o icc, 25o icc, 85o

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